Split detection system

ABSTRACT

A split detecting system for use in bowling comprised of a circuit of electronic logic gates formed of semiconductor elements and connected to determine the truth of the following logical expression: S 1(10 . 6 . 3 + 6 . 10 . 9 + 3 . 5 . 10 + 3 . 8 . 10 + 2 . 10 + 4 . 10 + 7 . 10 + 7 . 4 . 2 + 7 . 4 . 8 + 7 . 2 . 5 + 7 . 2 . 9 + 7 . 3 + 7 . 6 + 8 . 5 . 3 + 8 . 5 . 9 + 4 . 2 . 5 + 4 . 2 . 9 + 4 . 3 + 6 . 3 . 5 + 6 . 3 . 8 + 6 . 4 + 2 . 5 . 9 + 2 . 6 + 2 . 3) (1) where: S represents the presence of a split 1-10 REPRESENT STANDING PINS IN THEIR CONVENTIONAL POSITIONS, 1-10 REPRESENT DOWNED PINS IN THEIR CONVENTIONAL POSITIONS, THE SYMBOLS ( ) AND . REPRESENT AND functions, and THE SYMBOL + REPRESENTS AN OR function.

United States Patent 191 Russell et al.

[ June 11, 1974 ABSTRACT SPLIT DETECTION SYSTEM [57] [75] Inventors: Jack A. Russell, Muskegon, Mich; W i

Jerome E Walker, Kimand; James A split detecting system for use in bowling comprised Hardenbmok, Columbus both of a circuit of electronic logic gates formed of semiof Ohio conductor elements and connected to determine the truth of the following logical expressioni [73] Asslgnee: Brunswick Corporation, Chicago, 3 =T 1 3 +5- 10 9 5 10 lll. 8 -l0+2- l0+4*l)+7'lO+ 22 Filed: Jan.30,1967 fi 7-2-9+7-3+7-6+8-3-3+ 1 pp s-5-9+4'2-5+4-7-9+4-3 +6 --5+6--8+6-4+ 52 us. Cl. 273/54 c, 340/323 (I) [51] Int. Cl A63d 5/04 a [58] Field of Search 273/54 C, 54 D; 340/323 h S represents the presence of a split References Cited 1l0 represent standing pins in their conventional UNITED STATES PATENTS pgsitions, 3,295,849 l/l967 Miller et al. 273/54 c 110 represent downed P in their Conventional 3.375.352 3/l968 House et al. 273/54 c X positions, 3,6372! 1 H1972 Helbig et al 273/54 C the symbols and represent AND functions, and 3,649,014 3/l972 Hoffman 273/54 C 3,649,015 3/1972 Reynolds 273/54 C the represents an function Primary Examiner-Anton O. Oechsle Attorney, Agent, or Firm-Hofgren, Wegner, Allen, Stellman and McCord; Donald S. Olexa; Sheldon S.

Epstein 12 Claims, 3 Drawing Figures 1! W5 l 6 7m [g7 BUFFS m 7 z 1% G19 P5 P98 51! P2 7 Fez/ et,

J 9PD 3 796 9 a e 975 4 l ,9

7,91 jZv SPLIT DETECTION SYSTEM BACKGROUND OF THE INVENTION While the occurrence of a split in a bowling game has long been recognized, until recently there has not been devised a system for automatically detecting and indicating the occurrence of a split. Certainly, the trends towards automation in bowling, and specifically, towards the use of equipment that eliminates possibilities of human error such as automatic foul detecting equipment, automatic scoring and recording equipment, automatic pinfall indicating equipment, etc., indicates the desirability of providing means for recognizing the occurrence of a split.

During the history of bowling, splits have been defined in different ways. For example, some bowlers consider that a split exists when, after the first ball in a frame has been rolled, the head pin is down and at least two pins remain standing with a sufficient distance between them such that a ball may pass freely through the space. A more encompassing definition is based on the fact that the standard equilateral triangular array of pins on a bowling lane as viewed from the approach of a bowling lane includes seven rows of pins, each row having one or two pins therein. Based on this observation, the definition suggests that a split exists when, after the first ball in a frame has been rolled, the head pin is down and pins remain standing in at least two of the seven rows, and at least one row having no pins standing separates the two rows having standing pins therein. An even more expansive definition of a split is offered by the American Bowling Congress. For example, in its Constitution, Specifications and Rules: for the 1962-63 season, copyright 1962, a split was defined as follows. A split shall be a set-up of pins remaining standing after the first ball has been legally delivered provided the head pin is down, and (l) at least one pin is downed between two or more pins which remain standing, as for example: 79, 3-10. (2) At least one pin is downed immediately ahead of two or more pins which remain standing, as for example: 5-6."

If the above mentioned American Bowling Congress split identifying conditions (1) and 2) are interpreted in the disjunctive, a total of 461 pin standing arrays will be designated as splits. However, only 459 standing arrays are so identified in this disclosure. Although the standing array of the 2, 4, 5, 7 and 9 pins and the array consisting of the 3, 5, 6, 8 and 10 pins might be regarded as splits under the disjunctive interpretation, they are herein regarded as non-split.

In a pending application assigned to the assignee of the instant application, a split detection system using the second definition listed above is disclosed. The actual means used to provide split detection include a scanning device having a wiper that scans a plurality of electrical contacts arranged in a precise geometrical configuration as the heart of the system. In another pending application assigned to the assignee of the instant invention, there is disclosed a split detection system which is capable of detecting and indicating any arrangement of standing pins that constitutes a split within the American Bowling Congress definition thereof as set forth above. In actuality, the latter system detects all possible non-splits and is constructed such that when a non-split is not detected, a split is indicated. The last mentioned device utilizes a plurality of notched bars, each corresponding to a pin together with a plurality of sensing bars that may enter aligned notches in the bars corresponding to the pins for purposes of split detection.

Since the systems referred to are mechanical or electromechanical in nature, possible disadvantages of mechanical or electromechanical constructions may be present. For example, sticking in the mechanical movements, or pitting and frictional wear in mechanically scanned electrical contacts may cause failure of the system. Furthermore, because of the mechanical or electromechanical nature of such systems, the various parts therefor must be specially fabricated, a factor which to some extent renders the systems economically more costly than might be desirable.

SUMMARY OF THE INVENTION The primary object of the invention is to provide a new and improved split detection system.

More specifically, it is an object of the invention to provide a split detection system which is not subject to possible failure by the wear normally associated with mechanical and electromechanical devices.

Another object is the provision of a split detection system which may be easily fabricated from shelf items such as standard electronic components or relays.

Yet another object is the provision of a split detection system including means for detecting the configuration of standing or downed pins and in response to such detection, providing an indication of a split if a split according to any one of the above definitions exists, the detecting means being comprised of a plurality of electrical logic gates.

A still further object is the provision of a split detection system such as that described in the preceding paragraph wherein the electrical gates are arranged to imp emeglm f wig ssa qal..ga res i= S represents the presence of a split,

l-lO represent standing pins in their conventional positions,

T-lO represent downed pins in their conventional positions,

the symbols and represent AND functions, and

the symbol represent an OR function.

Yet another object of the invention is the provision of a split detection system utilizing a plurality of electronic logic gates such that the system is virtually wholly electronic in nature.

Other objects and advantages of the invention will become apparent from the following description taken in conjunction with the accompanying drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic of a signaling circuit that may be used to provide the split detection system with information relative to pinfall;

FIG. 2 is a block diagram of electrical logic gates for digesting pinfall information and determining whether a split exists; and

FIG. 3 is a schematic illustration of one form of an electronic gate that may be used in constructing the logic illustrated in FIG. 2.

SPECIFIC DESCRIPTION It will be obvious from. the various foregoing definitions of a split, that the various definitions are not mutually inclusive of each other. As will be apparent to those skilled in the art, the first definition, relating to standing pins spaced a sufficient distance so as to permit the ball to pass freely therebetween, is the narrowest definition while the second definition is of significantly greater scope. Finally, it will be apparent that the definition offered by the American Bowling Congress is of the greatest scope and includes any split within the other two definitions. Accordingly, it is desirable that the split detecting system of the instant invention detect any split within any of the above definitions and thus it is necessary that the split detection system detects any split within the definition set forth by the American Bowling Congress. Furthermore, in view of the well-known control exercised over the sport of bowling by the American Bowling Congress, it is all the more desirable to detect any split within the definition set forth by that group.

It will be apparent from the foregoing definition of the American Bowling Congress that there are a number of possible standing pin arrays that constitute a split. Mathematical computation will illustrate that there are 1,024 possible pin combinations following the first ball including the situations wherein all pins are standing and no pins are standing. The fact that the definition bars the existence of a split when the head pin is standing eliminates half of these combinations. Of the remaining 512 combinations of pin arrays, one may be eliminated as being all pins down or strike situation. An additional 52 combinations are non-split combinations and comprise nine combinations wherein only one pin is standing and 43 combinations wherein two or more pins are standing but are not spaced to comprise a split.

The remaining 459 combinations are splits within the American Bowling Congress definition, and in practice it has been found that every one of the 459 combinations are encompassed by 24 basic split combinations, the remaining 435 being immaterial variations of at least one of the 24 basic combinations.

According to the present invention, a split detection system is based on a logical equation that will be true when any one of the basic 24 combinations of standing and downed pins is arranged in a pattern constituting a split within the American Bowling Congress definition. The logical equation, in conventional Boolean notation, is as follows:

S represents the presence of a split,

l-l0 represent standing pins in their conventional positions,

l-l 0 represent downed pins in their conventional positions,

the symbols and represent AND functions, and

the symbols} f, and represent AND functions, i

and the symbol -F represents an OR function. The system is comprised of electrical components arranged to detect the truth of the equation. It has been found that a relatively simple apparatus results when the truth of the simplified logical equation is detected.

In order to implement the system, it is necessary to provide a signaling system for generating information relative to each pin position with regard to whether the corresponding pin is standing or down. Referring to FIG. 1, there is seen a pin supporting surface, generally designated 11, of a conventional bowling lane. Near the rear end 12 of the surface 11, there are 10 pinspots 14 which are numbered from 1-l0 beginning with the front pin or head pin and consecutively from left to right in each transverse row as viewed from the front of the lane. The pinspots 14 are arranged in the form of an equilateral triangular which has a base parallel to the rear end 12 of the lane.

Pin detecting means in the form of switches PSl-PSIO are physically related to the corresponding pinspots for detecting whether a pin at a corresponding pinspot is standing or fallen. The pin detecting switches PSl-PSlO may be of the general form disclosed in Torresen et al application, Ser. No. 50,542, filed Aug. 18, 1960, now U.S. Pat. No. 3,278,186, and assigned to the same assignee as the instant application, and are arranged on the pin deck of an automatic pinsetter in the manner disclosed in that application.

When the pin detecting switches PS 1-PS10 are to be used with an automatic bowling score computer apparatus such as that disclosed in the copending application of Walker, U.S. Ser. No. 612,665, filed concurrently herewith, now U.S. Pat. No. 3,550,939, issued Dec. 29, 1970, and assigned to the same assignee as the instant application, they are normally closed and arranged to be opened by the presence of a standing pin at the corresponding pinspot during the detecting stroke of an automatic pinsetter. By means to be described, the opening of one of the switches PS l-PSIO issues a signal representative of a standing pin while the failure of one of the switches PSl-PSl0 to open issues a signal corresponding to a downed pin. Since the signal issuing system for each of the switches PSl-PSIO is identical, only one will be described. Such a system is schematically illustrated in conjunction with the switch PS7 in FIG. 1. One side of the switch PS7 is connected to ground while the other side is connected through a resistor 16 to a l2 volt source of power. The junction 18 of the resistor 16 and the switch PS7 is the point from which the two signals are taken to the remainder of the system.

From the foregoing, it will be apparent that when the switch PS7 is closed corresponding to a downed pin, thepotential at the junction 18 will be equal to 0 volts, a 0 volt potential corresponding to a downed pin signal. However, when the switch PS7 is opened corresponding to a standing pin, no current will be drawn and accordingly there is no voltage drop across the resistor 16 and the potential at thejunction 18 will swing to the potential of the source of power, here l2 volts. Thus, a potential of l 2 volts corresponds to a standing pin signal.

An input to a buffering and gating system 20 is taken from the junction 18. For the specific details of the buffering and gating system 20, reference may be made to the aforementioned copending application of Walker.

The buffering and gating system 20 is not essential to use of a split detection system according to the instant invention and, in fact, is only required when a single computing apparatus is used to score simultaneously two or more lanes. An output from the system 20 is utilized as an input to a conventional flip-flop PR7 which forms one bit of a pinfall register disclosed in said Walker application.

The flip-flop PR7 is a bi-stable multivibrator having a pair of interconnected sections that are arranged to alternatively conduct. When one section of the flip-flop conducts, it turns the other section off and vice versa. As is well known in the art, a flip-flop is referred to as being set" when one section is conducting and as reset when the other section is conducting. In the exemplary embodiment, a l2 volt signal is used to set the flip-flops although, depending upon the construction of the flip-flops, it will be apparent that a 0 volt signal could be used for the same purpose. In FIG. 1, the section that conducts when the flip-flop PR7 is set is schematically designated as the circle having a l therein, and it is referred to as the set section while the section that conducts when the flip-flop PR7 is reset is shown as the intersecting circle having a 0 therein, and it is referred to as the reset section".

The output of the buffering and gating system 20 is utilized as an input to the set section of the flip-flop PR7 to cause the latter to become set corresponding to a standing pin. The arrangement of the flip-flop PR7 is such that when it is set, the output from the set section thereof, designated 7 PS, will have a 0 volt signal thereon while the output from the reset section, designated 7PD will have a l 2 volt signal thereon. When the flip-flop PR7 is reset, the 7PS output will be at -l 2 volts while the 7PD output will be at 0 volts. In order to periodically reset the flip-flop PR7, an input to the reset section thereof is adapted to receive a PINFALL REGISTER RESET signal from the computing apparathe aforementioned apsociated PD lead corresponds to a downed pin. In other words, either lead can provide a signal representative of the presence or absence of a corresponding standing pin, and as will become apparent, the particular lead chosen in any given instance depends on the voltage level desired at a particular point for representing a particular pin situation. Thus, a pin standing signal may be taken from a PD lead for convenience.

As seen in FIG. 2, the logical equation set forth above may be implemented with a plurality of logic gates such as the NOR gates shown. For clarity, the particular log ical function perfonned by each NOR gate is indicated by a (AND function) or a (OR function) in a corner thereof. Specifically, a NOR gate 22 is utilized to provide an AND function for combining the one pin down requirement with the remainder of the expression. A NOR gate 24 provides an OR function for the six basic expressions within the outer brackets of the above equation. NOR gates 26, 28, 30, 32, 34 and 36 implement the first expression within the brackets while NOR gate 38, 40, 42, 44, 46 and 48 implement the second expression within the brackets. The NOR gate 26 together with a NOR gate 50 implement the third expression, the NOR gates 38 and 40 together with NOR gates 58 and 60 implement the fourth expression, the NOR gate 34 together with NOR gates 52, 54 and 56 implement the fifth expression, and NOR gates 62, 64 and 66 implement the last expression.

Turning now to FIG. 3, there is seen aconventional form of a NOR gate that may be used in constructing the logic formed by the NOR gates 22-66. A transistor 68 has its emitter connected to ground and its collector connected through a resistor 70 to a l 2 volt source of power. The junction between the resistor 70 and the collector of the transistor 68 provides an output terminal 72. The base of the transistor 68 is connected through a resistor 74 to a +6 volt source of power and is additionally connected through a resistor 76, which may have a value of about one-third of that of the resistor 74, to the anodes of a plurality of diodes 78, the number ofdiodes 78 being dependent upon the number of inputs required of the NOR gate. The cathodes of the diodes 78 are connected to input terminals on which signals may be received from the signaling system illustrated in FIG. 1 or from others of the NOR gates illustrated in FIG. 2.

It will be apparent that when a 12 volt signal is placed on any one of the input terminals 80, current will flow from the +6 volt source through the resistor 74, the resistor 76 and the corresponding diode 78; and because of the relation of the values of the resistances 74 and 76, a negative potential will be applied to the base of the transistor 68. This will cause the transistor 68 to begin to conduct and as a result the output terminal will be at approximately 0 volts. However, if all of the input terminals 80 are at 0 volts, current will not flow through the resistors 74 and 76, and as a result, the base of the transistor 68 will be maintained at about +6 volts and will not conduct. Accordingly, there will be substantially no conduction through the resistor 70 and output terminal 72 will be at a potential of approximately l2 volts.

An example of the operation of the logic provided by the NOR gates 22-66 for the 2-6 split is as follows. The assumed split condition requires that the No. 2 and No. 6 pins be standing while No. 1, Nos. 3-5 and Nos. 7-10 are downed. In order to simplify an understanding of the electronic conditions present at each of the NOR gates 22-64, the following table, Table I, indicates the potentials applied as inputs from the signaling system shown in FIG. 1 to the logic circuit using the NOR gates 22-66.

In order to simplify discussion of the happenings at each gate, volt outputs or inputs willbe termed plus while l2 volt inputs or-outputs will be termed minus.

As will be apparent from Table 1 above, both inputs to the gate 26, which performs on OR function, will be plus and accordingly, the output of the gate 26 will be minus. The gate 28 performs an AND function and will have both of its inputs minus, one coming from the NOR gate 26 and the other from the signaling system. As a result, the output-of the gate 28 will be plus. The gate 30, which performs an OR function, will have a minus signal on lead 2PD and plus signals on the two other inputs thereof which are connected directly to the signaling system together with plus inputs from the gate 28 and thegate 36. In this last respect, it will be apparent that the gate 34, which performs an OR function, will have plus inputs and a minus output and that the gate 36 which performs an AND function will receive a minus input from the gate 34 and a plus input from the signaling system. Thus, the output of the gate 36 will indeed be plus. Returning to the gate 30, a minus input on lead 2PD requires that the output be plus, and as a result, the gate 32, which performs an AND function, has a plus input therefrom. A minus inputto the gate 32 is received from the signaling system on lead PS. The resulting plus output from the gate 32 is utilized as an input to the gate 24 and the response of the latter to the output of the gate 32 will be discussed hereinafter.

Turning now to the gate 38, it will be apparent that both of the inputs thereto are plus and accordingly the output will be minus. It will be noted that the gate 38 performs an OR function. The gate 40 will receive a minus input from the gate 38 together with a minus input from the signaling system, and as a result its output will be plus. The gate 40 performs an AND function. The gate 46, which provides an OR function, has a plus at SPD and a minus input at 2PD and a resulting plus output which is utilized as an input to the gate 48, which provides an AND function. As a result two plus inputs, the output of the gate 48 will be minus. The gate 42 provides an OR function and receives a plus input from the gate together with a plus input from the output of the signaling system at 3PD. However, gate 42 receives a minus input from gate 46, and on the 6PD input to the gate 42, a minus potential will be applied, and accordingly the gate 42 will have a plus output which is utilized as an input to a gate 44 which performs an AND function. The gate 44 receives a minus input from the signaling system at 7PS and as a result has a plus output which is fed to the gate 24.

The gate performs an AND function and also provides a plus input to the gate 24 as a result of a minus input from the gate 26 as well as a minus input from the signaling system and a minus signal at 8P8.

The gate 52 receives a minus input from the gate 34, and as a result its output is plus. This plus output is fed as an input to the gate 54 together with a second plus input from the signaling system to cause the gate 54 to have a minus output. The minus output from the gate 54 is fed as an input to the gate 56, and as a result the latter has a plus output which is fed to the gate 24. The

gates 52, 54 and 56 perform AND, OR and AND functions, respectively.

The gate 58 receives a plus input from the gate 40 together with a plus input from the signaling system and as a result has a minus output. A gate 60 senses the minus output from the gate 58 together with a minus output from the signaling system and as a result feeds a plus input to the gate 24. The gates 58 and 60 perform OR and AND functions, respectively.

The gate 62, which provides an AND function, receives a minus input on the 9PS lead from the signaling system and a plus input from the SPD input from the signaling system. As a result, the output of the gate 62 is plus and this potential is sensed by the gate 64. The

gate 64 performs an OR function and receives a secondplus input from the signaling system on its 3PD input and a minus input from the signaling system on the 6PD lead..As a result, the output ofthe gate 64 is plus. The gate 66, which provides an AND function, receives a first input from the gate 64 which, it will be recalled, is plus and a second plus input from the 2P8 output of the signaling system. As a result, the gate 66 provides the gate 24 with its first minus input.

The gate 24 having a single minus input will have a plus output which is fed to the gate 22. The gate 22 provides an AND function and receives a second plus input from the lPD output from the signaling system. Accordingly, the gate 22. will have a minus output which, in the exemplary embodiment of the invention, corresponds to the existence of a pattern of pins corresponding to a split.

It will, of course, be obvious that in order for the gate 22 to have a minus output corresponding to the existence of a split pattern, both of the inputs to the gate 22 must be plus. The direct input from the signaling system, the lPD lead, will only carry a plus potential when the one pin is downed. The second input to the gate 22 will only carry a plus potential when the gate 24 has at least one minus input. It will be recalled that the first five inputs to the gate 24 were positive and therefore, could not have caused the ultimately resulting split signal. Therefore, it will be apparent that the conditionresulting in a split signal must have been detected in the gates 62, 64, and 66, and more particularly, that the two conditions were the minus input to the gate 64 on the 6PD lead and the plus input to the gate 66 on the 2P5 lead. It will also be apparent that the gates 64 and 66.implement the 2 and 6 portion of the last expression in the preceding equation.

An examination of the logic provided by the gates 22-66 will indicate that the same basic happenings will occur any time a split under the American Bowling input if two split patterns'exist. For example, if a bowler left the No. 2, No. 6 and No. 7 pins standing, it willbe apparent that the 2-6 constitutes a split in and of itself and that the 2-7 constitutes a split in and of itself. The 2-6 split is detected by the gates implementing the last expression of the equation in the manner just described while the 2-7 split is detected by the gates 38-48 implementin g the second expression of the equation. As a result, the gate 24 will receive minus inputs both from the gate 66 and the gate 44.

In order to provide an indication of the occurrence of a split as detected by the logic formed by the gates 22-66, an indicating means, such as a lamp 82 is provided. Of course, it will be obvious that a signal for lighting the lamp 82 may be used to cause the'printing of a split symbol or energize any other type of indication means desired. The lamp 82 has one lead connected to ground and a second one connected to the emitter of a transistor 84. The emitter of the transistor 84 is also connected through a resistor 86 to ground while the collector of the transistor 84 is connected directly to a l 2 volt power supply. Thus, when the transistor is turned on it will be apparent that 12 volts will be applied across the lamp 82 to light the latter thereby providing a perceptible indication of the occurrence of a split. The base of the transistor 84 receives its bias from the output of an AND gate 88.which may be used when the split detection system is used in conjunction with a computer or an automatic pinsetter that is arranged to detect pins after both the first ball in a frame and the second ball in a frame. The AND gate 88 includes an input from the NOR gate 22 together with a second input on which an indication of whether the pinfall pattern just detected resulting from the rolling of the first ball in a frame or the second ball in a frame. The second input to the AND gate 88 may be taken from a bowling score computer or automatic pinsetter 90 in any suitable manner. One suitable connection is shown in the aforementioned application of Walker and is arranged to provide the AND gate 88 with a second minus input only when the pinfall occurred after the first ball in a frame. As a result, pin patterns detected after the second ball in a frame will not be indicated as splits as the AND gate 88 will be disabled by the signal from the computer andcannot turn on the transistor 84. A similar signal could also be taken from the usual first ball-second ball switch found in an automatic pinsetter 90 but is only necessary when the pinsetter detects pinfall after the second ball in a frame.

When the split detection is used in conjunction with a computer such as that described in the aforementioned Walker application, pinfall information is held a sufficiently long time in the pinfall register so as to enable printing of a split symbol. However, where an indicator such as the lamp 82 is utilized, it may be desirable to interpose a holding circuit between the AND gate 88 and the transistor 84 that operates to maintain the lamp 82 illuminated in a manner similar to the methods used for maintaining energization of pin position indicating lamps now commonly used in automatic pinsetters.

Returning to FIG. 1, there is seen a portion of a modified signaling system which may be used to provide the necessary potentials to the various ones of the gates 22-66. Since the modified arrangement is identical for each one of the pinspots, only one is described. Rather than using single contact switches such as PS l-PS8 and P810, a double contact switch, PS9, may be used. The switch PS9 includes a first, normally closed contact 92 and a second, normally open contact 94. The switch PS9 may be alternately closed through the contact 92 for a downed pin and through the contact 94 when a standing pin is encountered. A pair of resistors 96 and 98 have a common junction connected to a l2 volt source of power. The resistor 96 is also connected to the contact 94. It will be apparent that when the switch PS9 is closed through the contact 92, the potential at the contact 92 will be 0 volts, but when the switch PS9 is closed through the contact 94, the potential at the contact 92 will swing to 12 volts. Accordingly, the signals at the contact 92 will correspond exactly to those present at the output of the reset section of the flip-flop PR7 and a lead from the contact 92 serves as the 9PD output. When the switch PS9 is closed through the contact 94 corresponding to a standing pin, the potential thereat will be equal to 0 while if the switch PS9 is closed through the contact 92, the potential of the contact 94 will swing to l2 volts. Accordingly, the contact 94 provides the 9P5 output.

From the foregoing, it will be apparent that we have provided a split detection system utilizing a plurality of electrical gates providing AND' and OR functions. While the AND and OR functions required for split detection have been described as being performed by electronic NOR gates, it will be apparent to those skilled in the art that logic gates other than NOR gates could be used. Furthermore, it will also be apparent that other logical gating could be used in place of the electronic logic. It will also be recognized that while this system is capable of detecting any split within the definitions set forth hereinabove, including the broad definition of the American Bowling Congress, some applications of the invention may involve detection and indication of only certain commonly occurring splits such as the 5-7, 5-10, 2-7, 3-10, 6-7, 4-l0 and 7-10.

Finally, while the logical equations set forth herein are based on the detection of the existence of just one or more of the basic 24 split combinations, the remaining 435 split combinations being immaterial variations of the basic 24, it will be recognized that more than the basic 24 combinations could be detected if desired even though such detection would be redundant. For example, the first expression of Equation 1 which will be true if the No. 3 and No. 10 pins are standing while the No. l and No. 6 pins are downed in actuality covers 64 split combinations wherein the No. l and No. 6 are downed, the No. 3 and No. 10 pins are standing and various combinations of, or all of, the.No. 2, No. 4, No. 5, No. 7, No. 8 and No. 9 pins are standing or downed.

Thus, each of the 64 combinations could be detected although it is only necessary to detect one combination, the conditions of the No. 2, No. 4, No. 5, No. 7 No. 8 and No. 9 pins being immaterial to the basic combination, and the invention is intended to cover such reduntant detection, as for example, would be obtained of a logic circuit where constructed to detect the truth of a Boolean expression obtained by expanding Equation 1 above. 9

Having described specific embodiments of our invention, we do not wish to be limited to the specific construction set forth, but rather, to have our invention construed broadly according to the true spirit thereof as set forth in thefollowingclaims.

We claim:

1. For use in connection with a bowling game wherein a ball is rolled at a plurality of 10 pins placed respectively on spaced pinspots on a bowling lane and wherein a "split exists after a ball has been rolled if the head pin is down and there are any two or more other standing pins with sufficient space therebetween to permit the ball to pass freely, a split detection system I comprising, in combination: signaling means providing a plurality of simultaneous signals relative to each pin for indicating whether the pin is standing or down; electrical circuit means including a plurality of electrical logic gates operatively connected to said signaling means and responsive to simultaneous signals for any of said pins forproviding a split signal derived solely from the existence of any of said splits and without regard to the numerical sum of the standing pins; and means responsive to said electrical circuit means for indicating the occurrence of said predetermined combination of standing pins.

2. The split detection system of claim 1 wherein said plurality of electrical logic gates are comprised of semiconductor elements.

I 3. The split detection system of claim 1 wherein said signaling means comprises a plurality of pin detecting switches there being oneof said plurality of said pin detecting switches associated with each of said pinspots.

4. The split detection system of claim 1 furtherincluding means interconnecting said plurality of electrical logic gates such that some of said gates perform AND functions and others of said gates perform OR functions whereby said electrical circuit may provide said signal for the occurrence of any one of a plurality of predetermined combinations of standings pins thereby providing detection of a plurality of differing splits.

5. For use in connection with a bowling game having a plurality of frames wherein a first ball in each frame is rolled at 10 pins placed respectively on spaced pinspots arranged in an equilateral triangular pattern on a bowling lane with a base of the pattern transverse to the bowling lane and wherein a split exists if the head pin is down and there are any two or more other standing pins with sufficient space therebetween to permit the ball to pass freely after a first ball in a frame has been rolled, a split detection system comprising, in combination signaling means providing a plurality of simultaneous signals including at least two for each pinspot, one indicative of the presence of a standing pin and another indicative of the absence of a standing pin, electrical circuit means including a plurality of electrical logic gates comprising semiconductor elements operatively connected to said signaling means and responsive to simultaneous signals for any of said pins for providing a first signal derived solely from the existence of any of said splits without regard to the numerical sum of the standing pins which is indicative of the occurrence of said split and a second signal indicative of the absence of a split, and means responsive to said electrical circuit means for indicating the occurrence of a split.

. 6. A combination as defined in claim 5, wherein a split also exists if the head pin is down and at least one pin is down between any two or more other pins which remain standing, and said electrical circuit is constructed to provide a signal indicativeof the occurrence of any split.

7. A combination as defined in claim 5 wherein a split exists if the head pin is down and at least one pin is down immediately ahead of any two or more other pins which remain standing, and said electrical circuit is constructed to provide a signal indicative of the occurrence'of any split.

8. A combination as defined in claim 5 wherein the pins are numbered 1-10 beginning with the front pin and consecutively from left to right in each transverse row while facing the rear end of the lane, wherein a split is defined as any setup of pins remaining standing after the first ball has been legally delivered provided the head pin is down and (1) at least one pin is downed between any two or more pins which remain standing, as for example, the No. 7 and No. 9 pins, or the No. 3 and No. 10 pins, or (2) at least one pin is downed immediately ahead of any two or more pins which remain standing, as for example, the No. 5 and No. 6 pins, and said electrical circuit is constructed to provide a signal indicative of the occurrence of any split except where the setup of pins remaining after the first ball has been legally delivered consists of either the 2, 4, 5, 7 and 9 pins or the 3, 5, 6, 8 and 10 pins.

9. A combination as defined in claim 8 wherein said signaling means comprises a plurality of pin detecting switches associated respectively with said pinspots.

10. A combination as defined in claim 8 wherein a split exists whenever the following logical equation is 3- 8 10+2' 10+4- 1 0+7' 10+ 7'4-2+7-'4- +7-2-5+ 7-g'9+7-3+7-6+8'5-3+ 8-5-9+4-Z-5+4-2-9+4 -3+ 6'3-5+6'3-8+64+2'5-9+ 2 6 2 3) where:

8 represents the occurrence of a split, 1 19 represent standing pins, 1-10 represent downed pins, the parentheses and dots represent AND functions,

and the plus marks represent an OR function, 

1. For use in connection with a bowling game wherein a ball is rolled at a plurality of 10 pins placed respectively on spaced pinspots on a bowling lane and wherein a ''''split'''' exists after a ball has been rolled if the head pin is down and there are any two or more other standing pins with sufficient space therebetween to permit the ball to pass freely, a split detection system comprising, in combination: signaling means providing a plurality of simultaneous signals relative to each pin for indicating whether the pin is standing or down; electrical circuit means including a plurality of electrical logic gates operatively connected to said signaling means and responsive to simultaneous signals for any of said pins for providing a split signal derived solely from the existence of any of said splits and without regard to the numerical sum of the standing pins; and means responsive to said electrical circuit means for indicating the occurrence of said predetermined combination of standing pins.
 2. The split detection system of claim 1 wherein said plurality of electrical logic gates are comprised of semiconductor elements.
 3. The split detection system of claim 1 wherein said signaling means comprises a plurality of pin detecting switches there being one of said plurality of said pin detecting switches assOciated with each of said pinspots.
 4. The split detection system of claim 1 further including means interconnecting said plurality of electrical logic gates such that some of said gates perform AND functions and others of said gates perform OR functions whereby said electrical circuit may provide said signal for the occurrence of any one of a plurality of predetermined combinations of standings pins thereby providing detection of a plurality of differing splits.
 5. For use in connection with a bowling game having a plurality of frames wherein a first ball in each frame is rolled at 10 pins placed respectively on spaced pinspots arranged in an equilateral triangular pattern on a bowling lane with a base of the pattern transverse to the bowling lane and wherein a split exists if the head pin is down and there are any two or more other standing pins with sufficient space therebetween to permit the ball to pass freely after a first ball in a frame has been rolled, a split detection system comprising, in combination signaling means providing a plurality of simultaneous signals including at least two for each pinspot, one indicative of the presence of a standing pin and another indicative of the absence of a standing pin, electrical circuit means including a plurality of electrical logic gates comprising semiconductor elements operatively connected to said signaling means and responsive to simultaneous signals for any of said pins for providing a first signal derived solely from the existence of any of said splits without regard to the numerical sum of the standing pins which is indicative of the occurrence of said split and a second signal indicative of the absence of a split, and means responsive to said electrical circuit means for indicating the occurrence of a split.
 6. A combination as defined in claim 5, wherein a split also exists if the head pin is down and at least one pin is down between any two or more other pins which remain standing, and said electrical circuit is constructed to provide a signal indicative of the occurrence of any split.
 7. A combination as defined in claim 5 wherein a split exists if the head pin is down and at least one pin is down immediately ahead of any two or more other pins which remain standing, and said electrical circuit is constructed to provide a signal indicative of the occurrence of any split.
 8. A combination as defined in claim 5 wherein the pins are numbered 1-10 beginning with the front pin and consecutively from left to right in each transverse row while facing the rear end of the lane, wherein a split is defined as any setup of pins remaining standing after the first ball has been legally delivered provided the head pin is down and (1) at least one pin is downed between any two or more pins which remain standing, as for example, the No. 7 and No. 9 pins, or the No. 3 and No. 10 pins, or (2) at least one pin is downed immediately ahead of any two or more pins which remain standing, as for example, the No. 5 and No. 6 pins, and said electrical circuit is constructed to provide a signal indicative of the occurrence of any split except where the setup of pins remaining after the first ball has been legally delivered consists of either the 2, 4, 5, 7 and 9 pins or the 3, 5, 6, 8 and 10 pins.
 9. A combination as defined in claim 8 wherein said signaling means comprises a plurality of pin detecting switches associated respectively with said pinspots.
 10. A combination as defined in claim 8 wherein a split exists whenever the following logical equation is true S 1(10 . 6 . 3 + 6 . 10 . 9 + 3 . 5 . 10 + 3 . 8 . 10 + 2 . 10 + 4 . 10 + 7 . 10 + 7 . 4 . 2 + 7 . 4 . 8 + 7 . 2 . 5 + 7 . 2 . 9 + 7 . 3 + 7 . 6 + 8 . 5 . 3 + 8 . 5 . 9 + 4 . 2 . 5 + 4 . 2 . 9 + 4 . 3 + 6 . 3 . 5 + 6 . 3 . 8 + 6 . 4 + 2 . 5 . 9 + 2 . 6 + 2 . 3) where: S represents the occurrence of a split, 1-10 represent standing pins, 1-10 represent downed pins, the parentheses and dots represent AND functions, and the plus marks represent an OR function, and said logic gates are interconnected to follow said logical equation and simplifications and expansions thereof.
 11. A combination as defined in claim 10 wherein said logic gates comprise NOR gates, some connected to perform AND functions and the others connected to perform OR functions.
 12. The combination as defined in claim 10, wherein the following logical equation is true: S 1 (10 (6 (3+9) + 3 (5+8) + 2 + 4 + 7) + 7 (4 (2+8) + 2 (5+9) + 3 + 6) + 8.5(3+9) + 4 (2 (5+9) + 3) + 6 (3 (5+8) + 4) + 2 (5.9 + 6 + 3)). 